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So after applying the 0 bit bit plane slicing on qij image the output image will be 2/8 of the original image i.e This will able to compressed the size of image to 25%. The main objective of this paper is to develop an efficient hardware on fpga chip for compression of an image using angular domain in order to optimize area, power and delay and. Implementation of image compression algorithm using salient features of this book include Four new image compression algorithms and implementation of these algorithms Fpga kit implementation based on the set partitioning in hierarchical trees coding algorithm and discrete wavelet transform is used for the compression of images. Currently, most hardware implementations of image compression are based on traditional image compression algorithms, such as jpeg In order to improve the performance of image. The proposed method is used to reduce the bit rate of the pixels for better image compression by using angular transformation Here propose an hardware efficient fpga architecture using. A programmable hardware platform, developed in the computer architecture laboratory at ucsb, was ch sen as a substrate for this project